The present invention is in the field of flash memory cells provided with split-gates and having a virtual ground arrangement.
Several patents have proposed to use split-gate arrangements in flash memory cells, e.g., U.S. Pat. No. 5,268,585, U.S. Pat. No. 5,338,952, U.S. Pat. No. 5,414,286, U.S. Pat. No. 5,587,332, U.S. Pat. No. 5,614,747, WO/99/13513, and JP-A-07/130884. Of these prior art documents, U.S. Pat. No. 5,338,952 also discloses a virtual-ground arrangement of such split-gate memory cells. This known virtual ground arrangement will be summarized below.
FIG. 1, which corresponds to FIG. 7 of U.S. Pat. No. 5,338,952, shows two split-gate memory cells C11, C12 in a virtual ground arrangement. Memory cells C11, C12 are built on a p-type Si substrate 1. Three n+ diffusion layers 8 are shown. The left-hand n+ layer 8 operates as a drain to memory cell C11. The middle diffusion layer 8 operates as a source to memory cell C11 and as a drain to memory cell C12. The right-hand diffusion layer 8 operates as a source to memory cell C12 (and may operate as a drain to a further memory cell, not shown, at the right-hand side of memory cell C12). Since adjacent memory cells share a source/drain diffusion layer, this arrangement is referred to as xe2x80x9cvirtual groundxe2x80x9d.
A first SiO2 gate oxide film 2 is present on the substrate 1 between a selection gate 4 and the substrate 1. A rather thick second insulating layer 5 of SiO2 is located on top of the selection gate 4. A floating gate 11 is located adjacent to the selection gate 4, and separated from the substrate 1 by a tunnel oxide film 9 made of SiO2. The floating gate 11 is surrounded by an insulating film to insulate the floating gate from any other conducting element.
On top of the entire structure, as shown in FIG. 1, a control gate 13 is formed.
FIG. 2, which corresponds to FIG. 6 of U.S. Pat. No. 5,338,952, shows an equivalent electric circuit of four memory cells C11, C12, C21, C22 in a virtual ground connection scheme. In FIG. 2, the following reference signs are used. Reference sign CG1 refers to a control gate line interconnecting control gates 13 of memory cells C11, C12 as shown in FIG. 1. Reference sign CG2 refers to a control gate line interconnecting control gates of memory cells C21, C22. Reference signs SG1 and SG2 refer to selection gate lines interconnecting selection gates of memory cells C11, C21, and C12, C22, respectively. Reference sign BL1 refers to a bit line interconnecting the drains of memory cells C11, C21. Reference sign BL2 refers to a bit line interconnecting both the sources of memory cells C11, C21 and the drains of memory cells C12, C22. Reference sign BL3 refers to a bit line interconnecting the sources of memory cells C12, C22.
For programming, erasing, and reading e.g. memory cell C21, the following voltages on the control gate lines CG1, CG2, the selection gate lines SG1, SG2, and the bit lines BL1, BL2, BL3 apply (Table 1).
Writing information into memory cells is carried out by means of the xe2x80x9cSource Side Injectionxe2x80x9d (SSI) current mechanism. Erasing memory cells is done by xe2x80x9cFolwer-Nordheinxe2x80x9d (FN) tunneling.
As already referred to in U.S. Pat. No. 5,338,952, a problem during reading memory cell C21 may arise due to over-erasure of memory cell C11. Over-erasure of memory cell C11 may occur during erasing cell C11 and refers to too large an amount of electrons being removed from the floating gate 11 such that, after the erasing procedure, floating gate 11 is effectively positively charged. Consequently, even though control gate line CG1 is not charged during reading memory cell 21, memory cell C11 may still be slightly conducting since its selection gate 4 is also positively charged owing to selection line SG1 being high. Thus, since bit line BL1 is high and bit line BL2 is low during reading memory cell C21, an undesired leakage current may flow through memory cell C11.
In order to solve this problem of over-erasure, U.S. Pat. No. 5,338,952 proposes to provide the individual memory cells with drain and source lines extending perpendicularly to one another, so that by generating suitable drain and source voltages only one desired memory cell will be selected.
Therefore, it is an object of the present invention to provide a split-gate memory cell that solves the problem of over-erasure and that can be connected in a virtual ground arrangement in which source and drain lines are still parallel to one another.
This object is obtained by means of a memory cell according to the invention, comprising:
(a) a semiconductor substrate provided with a first diffusion layer and a second diffusion layer on a substrate surface;
(b) a floating gate insulating film on the substrate surface and a floating gate on the floating gate insulating film;
(c) a selection gate insulating film on the substrate surface and a selection gate on the selection gate insulating film;
(d) a control gate insulating film on the substrate surface and a control gate on the control gate insulating film;
the floating gate, selection gate and control gate being electrically insulated from one another, the first and second diffusion layers being arranged as a source and a drain of a field effect transistor structure, and the floating gate and selection gate being arranged as series field effect gates in the field effect transistor structure, and the control gate being arranged as a further field effect gate in the field effect transistor structure, in series with both the floating gate and the selection gate.
It is observed that, in this definition, xe2x80x9cin seriesxe2x80x9d refers to the different gates being arranged such that they are able to generate conducting channels in series with one another between the drain and the source of the memory cell transistor structure.
Such a memory cell may be termed a xe2x80x9cthree transistor flash memory cellxe2x80x9d or a xe2x80x9cdouble-split-gate flash memory cellxe2x80x9d. The advantage of such a memory cell is that no conducting channel can be inadvertently generated between source and drain diffusion layers by an over-erased floating gate. It will always be necessary that the control gate voltage is also high enough to provide a conducting channel in the substrate below the control gate in series with the conducting channel in the substrate due to the selection gate voltage.
Advantageously, a plurality of such memory cells can be applied in a memory, wherein:
the memory cells are arranged in a plurality of rows and a plurality of columns, the rows extending in a row direction and the columns extending in a column direction;
the first diffusion layer extends in the column direction to form interconnected, combined sources and drains of adjacent columns of memory cells in the column direction;
the second diffusion layer extends in the column direction to form interconnected, combined sources and drains of adjacent columns of memory cells in the column direction;
selection gates of memory cells in a column of memory cells are interconnected by a selection gate line extending in the column direction;
control gates of memory cells in a row direction are interconnected by a control gate line extending in the row direction.
In such a memory, the sources of a column of memory cells are the drains of the memory cells of an adjacent column. Thus, the memory has a virtual ground structure. Moreover, the control gate line extends in a direction perpendicular to the source and drain lines, thus providing a unique selection of any memory cell during reading and avoiding that a conducting channel can be inadvertently generated between source and drain diffusion layers by an over-erased floating gate. For each individual memory cell, it will always be necessary that the control gate voltage is also high enough to provide a conducting channel in the substrate below the control gate in series with the conducting channel in the substrate due to the selection gate voltage.
The present invention also relates to a process for making a memory cell comprising the following steps:
(a) providing a semiconductor substrate of a first conductivity type;
(b) forming a selection gate insulating layer on the substrate;
(c) forming a first conducting layer on the selection gate insulating layer;
(d) forming an additional insulating layer on the first conducting layer;
(e) etching the additional insulating layer, the first conducting layer and the selection gate insulating layer to form a selection gate separated from the substrate by a selection gate insulating film and having an additional insulating film on top of it;
(f) forming a floating gate insulating layer;
(g) forming side wall spacers adjacent to the selection gate and separated from the selection gate by the floating gate insulating layer;
(h) providing first and second diffusion layers of a second conductivity type in the substrate using the side wall spacers and the additional insulating film as a diffusion mask;
(i) etching a portion of the side wall spacers at one side of the selection gate to form a floating gate from a remaining portion of the side wall spacer at an opposite side of the selection gate;
(j) forming a control gate insulating layer;
(k) forming a control gate on said control gate insulating layer.
This process is a simple alternative to the process proposed in FIGS. 3A-3E in U.S. Pat. No. 5,614,747. Instead of first removing side wall spacers at one side of the selection gate and then providing the substrate with diffusion layers, the process according to the invention exchanges these two steps such that a portion of the control gate will also form the gate of a field effect transistor structure in series with the field effect transistors formed by the floating gate and the selection gate.
In a similar way, the present invention also provides a method for making a memory provided with memory cells, the memory cells being arranged in a plurality of rows and a plurality of columns, the rows extending in a row direction and the columns extending in a column direction; the method comprising the following steps:
(a) providing a semiconductor substrate of a first conductivity type;
(b) forming a selection gate insulating layer on the substrate;
(c) forming a first conducting layer on the selection gate insulating layer;
(d) forming an additional insulating layer on the first conducting layer;
(e) etching the additional insulating layer, the first conducting layer and the selection gate insulating layer to form selection gates separated from the substrate by selection gate insulating films and having additional insulating films on top of them;
(f) forming a floating gate insulating layer;
(g) forming side wall spacers adjacent to the selection gates and separated from the selection gates by the floating gate insulating layer;
(h) providing diffusion layers of a second conductivity type in the substrate using the side wall spacers and the additional insulating films as a diffusion mask;
(i) etching portions of the side wall spacers at first sides of the selection gates to form floating gates from remaining portions of the side wall spacers at second sides opposite the first sides of the selection gates;
(j) forming a control gate insulating layer;
(k) forming a control gate layer on the control gate insulating layer;
(l) forming control gates in the control gate layer.
The memory cell according to the invention can advantageously be both programmed and deprogrammed via a Folwer-Nordhein tunneling process. To that end, the invention also relates to a method of either programming or deprogramming a memory cell, the memory cell comprising:
(a) a semiconductor substrate provided with a first diffusion layer and a second diffusion layer on a substrate surface;
(b) a floating gate insulating film on the substrate surface and a floating gate on the floating gate insulating film;
(c) a selection gate insulating film on the substrate surface and a selection gate on the selection gate insulating film;
(d) a control gate insulating film on the substrate surface and a control gate on the control gate insulating film;
the floating gate, selection gate and control gate being electrically insulated from one another, the first and second diffusion layers being arranged as a source and a drain of a field effect transistor structure, the floating gate and selection gate being arranged as series field effect gates in the field effect transistor structure, and the control gate being arranged as a further field effect gate in the field effect transistor structure, in series with both the floating gate and the selection gate, and the method comprising the following step:
applying predetermined voltages to the control gate, the selection gate and the first and second diffusion layers, such that the floating gate is either charged or discharged by Folwer-Nordhein tunneling.
During reading a memory cell, the cell is uniquely addressed by the control gate, thus avoiding over-erasure problems. To that end, the invention also relates to a method of reading a memory cell, the memory cell comprising:
(a) a semiconductor substrate provided with a first diffusion layer and a second diffusion layer on a substrate surface;
(b) a floating gate insulating film on the substrate surface and a floating gate on the floating gate insulating film;
(c) a selection gate insulating film on the substrate surface and a selection gate on the selection gate insulating film;
(d) a control gate insulating film on the substrate surface and a control gate on the control gate insulating film;
the floating gate, selection gate and control gate being electrically insulated from one another, the first and second diffusion layers being arranged as a source and a drain of a field effect transistor structure, the floating gate and selection gate being arranged as series field effect gates in the field effect transistor structure, and the control gate being arranged as a further field effect gate in the field effect transistor structure, in series with both the floating gate and the selection gate, and the method comprising the following step:
applying predetermined voltages to the control gate, the selection gate and the first and second diffusion layers, such that conducting channels are formed in the substrate surface between the first and second diffusion layers and below both the control gate and the selection gate.